This invention relates to non-volatile semiconductor memory devices and, more particularly, to a non-volatile semiconductor memory device such as electrically alterable read only memory (EAROM).
Hitherto, a commonly termed non-volatile semiconductor memory device which comprises a variable threshold value field-effect device using a gate insulation film having a charge storage function is well known in the art. There are available a metal-nitride-oxide-semiconductor (MNOS) device, a metal-alumina-oxide-semiconductor (MAOS) device and a dual-dielectric-charge-storage (DDC) device, and among these devices the MNOS device is extensively used in practice. For example, in an EAROM which uses these memory devices, memory storage characteristics, operating characteristics, bit density, etc. are important in performance.
The prior-art MNOS-EAROM products use P-channel MNOS devices. Usually, in the MNOS structure, those in which the flat band voltage is on the negative side can be more readily produced than those in which the flat band voltage is on the positive side, and in this respect the P-channel enhancement type MNOS device is advantageous compared to the N-channel enhancement type MNOS device for the former can be more readily manufactured than the latter. In an EAROM memory cell array using P-channel MNOS devices, each memory cell can thus be constructed without using a transistor for selection but merely by using a single MNOS device.
However, it is a fact that to date the memory cell using a P-channel MNOS device is too slow in operation to be able to sufficiently meet the recent demand for the high speed operation of the EAROM. While the N-channel MNOS devices are superior in the operation speed, they usually tend to be of the depletion type, and it is difficult to produce the enhancement type devices. With the depletion type, the threshold voltage is, for instance, +5 volts at the time of a high level state, -5 volts at the time of a low level state, and a prior-art memory cell array structure only one half the window of the threshold value, for instance, values between 0 and 5 volts, can be utilized. With the prior-art memory cell array structure a read-out voltage has to be impressed upon the gate of the MNOS device at the time of reading out information while it is well known that with the memory device of this type the impression of a gate bias voltage extremely deteriorates the memory storage characteristic. Therefore, limitations are imposed upon the number of times of the information read-out, and it is necessary to add a complicated refresh construction.
In order to solve the above problems, it has been proposed to provide an MOS selection transistor in series with an MNOS device within each memory cell, that is, to provide a two-transistor construction for each memory cell. Such a memory cell is disclosed, for instance, in "N-channel Si-gate MNOS Device for High Speed EAROM" announced by Yuji Yatsuda et al in the Digest of Technical Papers issued during the 10th Conference on Solid State Devices held in Tokyo on Aug. 29 through 30, 1978. FIG. 1 shows the construction of this memory cell. It has an N-channel MNOS device Q.sub.1 and an MOS selection transistor Q.sub.2, which are formed between a common N.sup.+ -type region and respective N.sup.+ -type regions formed in a P-type well 12 which is in turn formed in an N-type silicon substrate 11. The MNOS device Q.sub.1 has a structure including a silicon dioxide layer 16, a silicon nitride layer 17 and a polycrystal silicon layer constituting a memory gate electrode 18, these layers being formed in the mentioned order on the P-type well 12. The MOS selection transistor Q.sub.2 has a structure which is obtained by successively forming the silicon dioxide layer 16 and polycrystal silicon layer constituting a selection gate electrode 19.
With the construction of FIG. 1, however, it is inevitable that the area of the memory cell is large compared to the structure where a single transistor is formed for each cell, and thus it is impossible to increase the bit density. In addition, with this construction the breakdown voltage between the gate region 18 and source and drain regions 13 and 14 of the MNOS device Q.sub.1 and that between the regions 13 and 14 and the silicon substrate 11 are low. Particularly, dielectric breakdown of these portions is prone when erasing and writing information is repeated. As a solution to this problem it may be thought to make the source and drain regions of the MNOS device to have a high breakdown voltage structure. However, the high breakdown voltage structure usually increases the memory cell area, so that with the prior-art structure of FIG. 1 where both the source and drains 13 and 14 of the MNOS device Q.sub.1 it is inevitable that the memory cell area is extremely large.